What Is Goal One
My first goal is to get a retro CPU core on the FPGA board to do something called a "Free Run" - an activity documented on a real chip in this blog post.
Here's the concept - instead of connecting actual RAM or ROM to the CPU, you instead hard-wire the data lines so that the CPU sees the same value at every memory address. In the case of a free run, that value is a CPU instruction called a "NOP", for No Operation. This instruction tells the CPU to do nothing, move to the next memory location, and execute the instruction there.
Since the data lines are hard-wired with the value of NOP, the CPU will see NOPs everywhere. So, it will start at some location (more on that in a future post), move to the next location, and so on, until it reaches the end of its memory space. It will then roll around to to bottom of memory (location zero), and keep going around again, forever.
Why do this? Well, even though the CPU address lines aren't actually changing the data that the CPU is seeing, the address lines still happily increment. You can watch them do this, and seeing them bounce up and down shows the CPU is running.
And for some reason, mine isn't.
Here's a bit more about the FPGA chip and board that I'm using.
The FPGA I'm using is a Zynq-7000, model XC7Z010. The Zynq family is a really interesting series of chips. They combine, on the same silicon, an ARM processor (with varying speeds and numbers of cores), interfaces for a variety of physical devices, some general purpose I/O pins, and most importantly, FPGA functionality ("fabric"). For this project, I'm not using the ARM at all, and will only use a small bit of the I/O capabilities.
The software used to program this chip is called Xilinx Vivado HLx. If you're used to lightweight tool chains in the software development world, then the FPGA world will surprise you. Vivado requires 20+ GB on your hard drive, and the install process takes a long time. For this project, I downloaded and installed the latest, version 2018.2.
In the past, I've tried a couple of times to get a retro CPU core in Verilog or VHDL to simply compile under Vivado, and failed. But this time, I got a couple of different cores working, and even set up enough of a project to generate a bitstream and download it to the board. It didn't work, but this is still progress.
What Doesn't Work
I'm using a simple Verilog 6502 CPU core. As far as I can tell, the inputs are wired such that the CPU should run, and I also supplied a clock signal to the CPU to make it go. But the address lines aren't bouncing up and down - they are staying off. So, I've got some more work to do.
When creating FPGA designs, Real Hardware Engineers (which I am, most decidedly, not) write test benches and do simulations, using various tools that permit a digital design to be executed in software and debugged. Simulation and test benches are really important, and they're something I really haven't studied enough. My method (let's throw it on the board and see what sticks) is that of a hobbyist, and it's OK, but it might not get me through this project. So, digging further into the simulation and test bench abilities of Vivado may be my next step.
More to come...