Saturday, September 8, 2018

That time when I didn't smash my FPGA board into small pieces

As the old sports intro goes, there is the thrill of victory, and the agony of defeat.

Trying to learn how FPGAs work is obviously feasible, and many have succeeded in doing so, even without being a trained EE. However, I'm finding that it's not for the faint of heart. In my last blog post, I mentioned that I like to learn things in the deep end of the pool. That end of the pool can be exhausting, and you might splash a lot of water without making much forward progress.

But as things go, just when you think you're sinking, some kind, sharing soul on the Internet throws you a life preserver.

My goal for the current Retrochallenge is to get a retro CPU core working on my FPGA board, and have it run a simple program. Since that's been done before many times, and most of the work has already been open-sourced, it shouldn't be a heavy lift. But each FPGA board and development toolchain is different. There are breaking changes between versions of the FPGA vendor's tools. And, even more so than in the software development world, documentation can be terse or non-existent.

Some details - I'm trying to get the following to work:
  • A Zybo development board (original, revision B) with a Zynq-7000 XC7Z010 chip,
  • The Vivado HLx toolset, used to create solutions for Xilinx FPGAs,
  • A 6502 core, written in Verilog by Arlet Ottens, and
  • A simple 6502 program written on the above, proving that the 6502 core is functional

And it turns out, that in desperate Google searches, I found a project that does all of the above, and more.

From the work done on the "C64 on an FPGA" blog by Johan Steenkamp, I should be able to learn the necessary steps to get a 6502 running on my Zybo. The author not only does the work, but graciously teaches you how it works.

It's kind of cheating, but my goal is to learn, so I can build upon what I've learned. Good artists copy, great artists steal.

More to come...

No comments: